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(R)
L3234 L3235N
HIGHLY INTEGRATED SLIC KIT TARGETED TO PABX AND KEY SYSTEM APPLICATIONS
HIGHLY INTEGRATED SUBSCRIBER LINE INTERFACE KIT FOR PABX AND KEY SYSTEM APPLICATIONS IMPLEMENTS ALL KEY ELEMENTS OF THE BORSCHT FUNCTION INTEGRATED ZERO CROSSING BALANCED RINGING INJECTION ELIMINATES EXTERNAL RELAY AND CENTRALISED RINGING GENERATOR ZERO NOISE INJECTED ON ADJACENT LINES DURING RINGING SEQUENCE LOW POWER IN STANDBY AND ACTIVE MODES BATTERY FEED WITH PROGRAMMABLE LIMITING CURRENT PARALLEL LATCHED DIGITAL INTERFACE SIGNALLING FUNCTIONS (OFF HOOK, GND-KEY) LOW NUMBER OF EXTERNAL COMPONENTS INTEGRATED THERMAL PROTECTION INTEGRATED OVER CURRENT PROTECTION 0C TO 70C: L3234/L3235N -40C TO 85C: L3234T/L3235NT
HEPTAWATT ORDERING NUMBER: L3234
TQFP44 ORDERING NUMBER: L3235N
DESCRIPTION The L3234/L3235N is a highly integrated SLIC KIT targeted to PABX and key system applications The kit integrates the majority of functions required to interface a telephone line. The L3234/L3235N implements the main features of the broths function: - Battery Feed (Balanced Mode) - Ringing Injection - Signalling Detection - Hybrid Function
The Kit comprises 2 devices, the L3234 ringing injector fabricated in Bipolar in 140V Technology. Its function is to amplify and inject in balanced mode with zero crossing the ringing signal. The device requires an external positive supply of 100V and a low level sinusoid of approx. 950mVrms. The L3235N Line Feeder is integrated in 60V Bipolar Technology. The L3235N provides battery feed to the line with programmable current limitation. The two to four wire voice frequency signal conversion is implemented by the L3235N and line terminating and balance impedances are externally programmable. The L3234/L3235N kit is designed for low power dissipation. In a short loop condition the extra power is dissipated on an external transistor. The Kit is controlled by five wire parallel bus and interfaces easily to all the STLC5046 and STLC5048 CODECs. In Kit with STLC5048 (see fig 1) the line impedance synthesis and echo canceling are performed inside the CODEC.
December 2001
1/25
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V100 GND VCC VCC 0.1F VRING 1 GND VCC VDD VCC VSS ZS=4100 7 6 IL 18 38 RP1 D2 1N4007 RT 1M OVERVOLTAGE PROTECTION RING RP2 20 TIP 30 D1 1N4007 CAC 100F RP2 20 TIP ZAC 43 11 12 RING 30 RP1 44 22 RTF VPOL LIM 24 14 17 VSS AGND CVSS CVCC 2 VBAT CVB CGF 390nF 0.1F 0.1F VBAT 0.1F VSS RGF 39K RR 51K CR 4.7F CF 390nF RF 39K 39 35 REF GKF BASE VREG TEXT MJE350 VBAT ZA RX VFRO0 100F 100K ZB 10 40 9 31 25 27 28 32 3 13 20 34 TX 29 CAC SUB 0.1F CS VDD 10F 10F CS 4 2 7 4.7F VA 6 82 5 82 3 0.1F 0.1F
L3234 - L3235N
L3234
GND
VEE
DX
DR
FS
ABS TYPICAL LINE CARD APPLICATION
MCLK
TSX
STLC5048 L3235N
IO0 OH RNG SBY PUNEG GDK BGND VCC IO11 IO12(CS0) IO13(CS1) IO14(CS2) IO15(CS3) VFRO1 VFXI1 VFRO2 VFXI2 VFRO3 VFXI3
D98TL381
VFXI0 CTX 100nF
INT IO1 IO2 IO3 IO4
RES
CS
CCLK
SERIAL CONTROL PORTS
CO
CI
RLIM 9.1K to 35K
VCC
L3234 - L3235N
L3234 Solid State Ringing Injector
DESCRIPTION The L3234 is a monolithic integrated circuit which is part of a kit of solid state devices for the subscriber line interface. The L3234 sends a ringing signal into a two wires analog telephone line in balanced mode. The AC ringing signal amplitude is up to 60Vrms, and for that purpose a positive supply voltage of +100V shall be available on the subscriber card. The L3234 receives a low amplitude ringing signal (950mVrms) and provide the voltage/current amplification (60Vrms/70mA) when the enable input is active (CS > 2V). In disable mode (CS < 0.8V) the power consumption of the chip is very low (<14mW). The circuit is designed with a high voltage bipolar technology (VCEO > 140V / VCBO > 250V). BLOCK DIAGRAM
HEPTAWATT
The package is a moulded plastic power package (Heptawatt) suitable also for surface mounting.
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L3234 - L3235N
PIN CONNECTION (Top view)
7 6 5 4 3 2 1
OUT2 V100 OUT1 GND VCC CS VA
D94TL131
ABSOLUTE MAXIMUM RATINGS
Symbol V100 VCC VA CS Tj Tstg 5V Power Supply Voltage Low Voltage Ringing Signal (with V100 = 120Vdc) Logical Ring Drive Input Max. Junction Temperature Storage Temperature Parameter Positive Power Supply Voltage Value +120 5.5 1.4 VCC 150 -55 to +150
o o
Unit V V Vrms C C
OPERATING RANGE
Symbol V100 VCC VA Top Tjop High Power Supply Voltage Low Power Supply Voltage Low Voltage Ringing Signal Operating Temperature for L3234 Max. Junction Operating Temperature (due to thermal protection) Parameter Value 95 to 105 5 5% 600 to 950 within 10Hz - 100Hz 0 to 70 130 Unit V V Vrms C C
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
THERMAL DATA
Symbol Rth j-case Rth j-amb Description Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 4 50 Unit
o o
C/W C/W
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 4/25 Name VA CS VCC GND OUT1 V100 OUT2 Description Low Voltage Ringing Signal Input Logical Ring Drive Input +5V Low Power Supply Common Analog-Digital Ground Ringing Signal Output +100V High Power Supply Ringing Signal Output in Opposite Phase with Out1
L3234 - L3235N
of the L3234 Solid State Ringing injector when used with the L3235N Line Feeder.
OPERATION DESCRIPTION The Fig. 1 show the simplified circuit configuration Figure 1: L3234/L3235N Circuit Configuration
+100V
GND
+5V
C100
CVCC
TIP
A
CO1
V100 RO1 OUT1 RO2 OUT2 CS 5 6
GND 4
VCC 3
LINE TERMINALS RING
B
CO2
RINGING INJECTOR 7
L3234
1 CA VA VA
D94TL-L3235N
CS
2
LINE FEEDER
GND -VBAT
L3235N
EXTERNAL COMPONENTS LIST In the following table are shown the recommended external components values for L3234.
Ref. R01, R02 C01, C02 CA C100 CVCC Value 82 10F - 160V 4.7F - 10V 100nF - 100V 100nF Involved Parameter or Function Ringing Feeding Series Resistors Ringing Feeding De coupling Capacitors Low Level Ringing Signal De coupling Capacitor Positive Battery Filter +5V Supply Filter
When the ringing function is selected by the subscriber card, a low level signal is continuously applied to pin 1 through a de coupling capacitor. Then the logical ring drive signal CS provided by L3235N is applied to pin 2 with a cadenced mode. The ringing cycles are synchronised by the L3234 in such a way that the ringing starts and stops always when the analog input signal crosses zero. When the ringing injection is enabled (CS = "1"), an AC ringing signal is injected in a balanced
mode into the telephone line. When the ringing injection is disabled (CS = "0"), the output voltage on OUT2 raises to the high power supply, whereas on OUT1, it falls down to ground. The L3234 has a low output impedance when sending the signal, and high output impedance when the ringing signal is disabled In fig. 2 the dynamic features of L3234 are shown.
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L3234 - L3235N
Figure 2: Dynamic Features of L3234
DATA TRANSMISSION INTERFERENCE TEST The L3234 meet the requirements of the technical specification ST/PAA/TPA/STP/1063 from the CNET. The test circuit used is indicated below.
The measured error rate for data transmission is lower than 10-6 during the ringing phase. This test measures if during the ringing phase the circuit induce any noise to the closer lines.
Figure 3: Test Circuit Data Transmission Interference Test
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L3234 - L3235N
ELECTRICAL CHARACTERISTICS (Test conditions: V100 = +100V, VCC = +5V, Tamb = 25C, unless otherwise specified) Note: Testing of all parameter is performed at 25C. Characterisation, as well as the design rule used allow correlation of tested performance with actual performances at other temperatures. All parameters listed here are met in the range 0C to +70C.
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig
STAND BY MODE: CS = "0"
IS (V100) IS (VCC) VSOUT1 VSOUT2 ZSOUT1 ZSOUT2 THD Consumption DC Output Voltage Output Impedance ZOUT Matching Harmonic Distortion During Emission VLINE < 6dBm; f = 1kHz -46 VA = 950mVrms; 50Hz VA = 950mVrms; 50Hz 92 70 70 15 -40 45 560 100 800 6 A A V V k k % dB 5 4
RINGING PHASE: CS = "1" DC OPERATION
IR (V100) IR (VCC) VROUT1 VROUT2 VIH IIH (CS = 0) VIL IIL (CS = 0) Ilim DC Line Current Limitation VA = 0V 70 Consumption DC Output Voltage Threshold Voltage on the Logical Input CS Z LINE = VA = 950mVrms; 50Hz VA = 0V VA = 950mVrms; 50Hz 44 44 2.0 1 0.8 1 150 2.5 2.2 5 3 56 56 mA mA V V V A V A mA 12 6
AC OPERATION
VOUT1/VA VOUT2/VA VOUT1 -VOUT1 THD VLINE ZIN (VA) ZOUT Ringing Gain Ringing Signal Harmonic Distortion Input Impedance Differential Output Impedance Z LINE = 2.2F + 1k VA = 0dBm ZLINE = 2.2F + 1k VA = 950mVrms; 50Hz VA = 950mVrms; 50Hz VA = 950mVrms; 50Hz ILINE < 50mArms 40 20 29.5 29.5 57 30 30 60 5 dB dB Vrms 7 % k 8 9 7
TEST CIRCUITS Figure 4.
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L3234 - L3235N
TEST CIRCUITS (continued) Figure 5.
VCC V100
CS 4.7F
2
3
6
7
VOUT2 82
10F/160V
B V ZLINE=600
L3234
1 4 5 VOUT1
10F/160V A 82 -VBAT 1M
GND LINE FEEDER VE 1KHz
D94TL133
Figure 6.
Figure 7.
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L3234 - L3235N
TEST CIRCUITS (continued) Figure 8.
Figure 9.
Figure 10.
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L3234 - L3235N
L3235N Subscriber Line Interface Circuit
DESCRIPTION Circuit description The L3235N Subscriber Line Interface Circuit (SLIC) is a bipolar integrated circuit in 60V technology optimized for PABX application. The L3235N supplies a line feed voltage with a current limitation which can be modified by an external resistor (RLIM). The SLIC incorporates loop currents, ground key detection functions with an externally programmable constant time. The two to four wires and four to two wires voice frequency signal conversion is performed by the L3235N and the line terminating and the balancing impedances are externally programmable. The device integrates an automatic power limitation circuit. In short loop condition the extra power is dissipated on one external transistor (Text). This aproach allows to assembly the L3235N in a low cost standard plastic TQFP44 package. The chip is protected by thermal protection at Tj = 150C. The SLIC is able to give a power up command for Combo in off hook condition and an enable logic for solid state ringing injector L3234. The L3235N package is 44 pin plastic TQFP. The L3235N has been designed to operate togheter with L3234 performing complete BORSHT function without any electromechanical ringing relay (see the application circuit fig. 16). ABSOLUTE MAXIMUM RATINGS
Symbol VBAT VCC VSS Tj Tstg Battery Voltage Positive Supply Voltage Negative Supply Voltage Max. Junction Temperature Storage Temperature Parameter Value -54 5.5 -5.5 150 -55 to +150 Unit V V V C C
TQFP44
PIN CONNECTION
VREG RING ZAC N.C. N.C. GKF
35
N.C.
N.C.
44
43
42
41
40
39
38
37
36
RTF
34 33 32 31 30 29 28 27 26 25 24 23
Vbat
TIP
N.C. AGND BGND N.C. N.C. CAC RPC N.C. TX ZB ZA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
N.C. GDK OH N.C. CS PU SBY N.C. RNG LIM N.C.
RX
VCC
REF
N.C.
N.C.
VSS
IL
N.C.
VPOL
N.C.
BASE
D99TL456
OPERATING RANGE
Symbol VBAT VCC VSS Top Tj Battery Voltage Positive Supply Voltage Negative Supply Voltage Operating Temperature for L3235N Max Junction Operating Temperature Parameter Min. -52 4.75 -5.25 0 Max. -24 5.25 -4.75 70 130 Unit V V V C C
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
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L3234 - L3235N
THERMAL DATA
Symbol Rth j-amb Description Thermal Resistance Junction-ambient Max Value 60 Unit C/W
PIN DESCRIPTION
N 1,4,5,8, 15,16,19 ,21,23, 26,30,33 ,36,37, 41,42 2 3 6 7 9 10 11 12 13 14 17 18 20 22 24 25 27 28 29 31 32 34 35 38 39 40 43 44 Name NC Not Connected Description
AGND BGND CAC RPC TX ZB ZA RX VCC REF VSS IL VPOL BASE LIM RNG SBY PU CS OH GDK RTF GKF TIP Vbat RING ZAC VREG
Analog/Digital Ground. Battery Ground. This is the Reference for the Battery Voltage (note 1). AC Current Feedback Input. External Protection Resistors AC Transmission Compensation. Four Wire Transmitting Amplifier Output. Non Inverting Operational Input Inserted in the Hybrid Circuit for 2W to 4W Conversion. The Network Connected from this Pin to Ground shall be a copy of the Line Impedance. VRX Output Buffer 2W to 4W Conversion. High Impedance Four Wire Receiving Input. Positive 5V Supply Voltage. Voltage Reference Output; a Resistor Connected to this pin sets the Internal Bias Current. Negative 5V Supply Voltage. Transversal Line Current Feedback Divided by 50. Non Inverting Operational Input to Implement DC Character. Driver for External Transistor Base. Voltage Reference Output; a Resistor Connected to this Pin Sets the Value of Line Current Limitation. Ringing Logic Input from Line Card Controller. Stand by Logic Input (SBY = 1 Set Line Current Limitation at 3mA). Power u.p Logic Output for the Codec Filter. (PU = 0 means Codec Filter Activated) Ring Injector Enable for L3234 Output. (CS = 1 means L3234 Ringing Injection Enable). Hook Status Logic Output (OH = 0 means off hook). Ground Key Status Logic Output (GDK = 0 means Ground Key on). Time Constant Hook Detector Filter Input. Time Constant GK Detector Filter Input. Tip Wire of 2 Wire Line Interface. Negative Battery Supply Input. RING wire of 2 Wire Line Interface. Non Inverting Input of the AC Impedance Synthesis Circuit. Emitter Connection for the External Transistor.
Note 1: AGND and BGND pins must be tied together at a low impedance point (e.g. at card connector level).
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L3234 - L3235N
L3235N FUNCTIONAL DIAGRAM
FUNCTIONAL DESCRIPTION DIGITAL INTERFACE The different operating modes of the L3235N are programmed through a digital interface based on two input pins: 1)SBY input programs the stand-by or Active/Ringing modes. 2)RNG input programs the ringing ON/OFF activation condition for the L3234. The L3235N digital interface has four output pins : 1)OH provides the on hook/off hook or ring trip informations (active low). 2)GDK provides the ground key on/off information (active low). 3)PU must be connected to the enable input pin of CODEC/FILTER devices like ETC 5054/57
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and automatically activates this device when in active mode off-hook is detected or when ringing mode is selected. 4)CS output must be connected to the CS enable input of the solid state ringing injector L3234. In this way the L3234 will be enabled when ringing mode is programmed and will be automatically disabled when the ring trip condition will be detected reducing the ringing signal disconnection time after ring trip. The table 1 here below resumes the different operation modes and the relative logic output signals. The two current detection (hook and GND key) have internal fixed threshold. Externally it is possible to program their time costant through two R-C components connected respectively to pin 26 (RTF) and pin 27 (GKF).
L3234 - L3235N
Table 1.
OPERATING MODE INPUT PIN SBY 0 0 0 0 0 0 0 0 1 1 RNG 0 0 0 0 1 1 1 1 0 1 LINE STATUS 0: ON HOOK 1: OFF HOOK 0 0 1 1 0 0 1 1 X X 0: NO GND KEY 1: GND KEY ON 0 1 0 1 0 1 0 1 X X OH 1 0 0 0 1 0 0 0 1 1 OUTPUT PIN GDK 1 0 1 0 1 0 1 0 1 1 PU 1 0 0 0 0 0 0 0 1 0 CS 0 0 0 0 1 0(*) 0(*) 0(*) 0 1
ACTIVE
RINGING
STAND-BY
(*)This status is latched and doesn't change until RNG turn to 0
OPERATING MODES Stand-By (SBY = 1 and RNG = 0) In Stand-By mode the L3235N limits the DC Loop current to 3 mA. In this mode all the AC circuits are active and all the AC characteristics are the same as in Active Mode. Also the two Line Current detectors (hook and GND key) are active but due to the loop current limited to 3 mA they will not be activated. This mode is useful in emergency condition when it is very important to limits the system power dissipation. Ringing Mode (SBY = 0 and RNG = 1) When ringing mode is selected "CS" pin is set to 1 in order to activate the L3234 ringing injector. See L3234 for detailed description. Ring trip is detected by means of the same internal circuitry used for off-hook detection. An off-hook delay time lower than 12 FRING should be selected. (see ext. components list). When ring trip is detected "CS" is automatically set to "0" allowing in this way a quick ringing disconnection. After Ring trip detection the Card Controller must set the L3235N in active mode to remove the internal latching of the "CS" information.
Active mode (SBY = 0 and CS1 = 0) In Active mode the L3235N has the DC characteristic show in Fig.13 The DC characteristics of L3235N has two different feeding conditions: 1)Current Limiting Region : (short loop) the DC impedance of the SLIC is very high (>20 Kohm) therefore the system works as a current generator. By the ext. resistor RLIM connected at pin 19 it is possible to program limiting current values from 20 mA to 70 mA. 2) Voltage source region (long loop). The DC impedance of the L3235N is almost equal to zero therefore the system works like a voltage generator with in series the two external protection resistors Rp. When a limiting current value higher than 40 mA is programmed the device will automatically reduce to 40 mA the loop current for very short loop. This is done in order to limit the maximum power dissipation in very short loop to values lower than 2W for the external transistor and lower than 0.5W for the L3235N itself. This improve the system reliability reducing the L3235N power dissipation and therefore the internal junction temperature.
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L3234 - L3235N
Figure 11: DC characteristic in Active Mode with two different values of limiting current (30mA and 70 mA).
Figure 12: Line current versus loop resistance with two different values of limiting current (30mA and 70mA)
AC transmission circuit stability To ensure stability of the feedback loop shown in block diagram form in figure 13 two capacitors are required. Figure 14 includes these capacitors Cc and Ch.
AC - DC separation The high pass filter capacitor CAC provides the separation between DC circuits and AC circuits. A CAC value of 100mF will position the low end frequency response 3dB break point at 7Hz, fsp = 1 2 220 CAC
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L3234 - L3235N
Figure 13.
Cac
Cac 6 18 IL/50 IL'/50 RX Vrx 12 38 TIP +1 Zl X2 40 RING Eg -1 RP Vl RP IL
+
TX Vtx
9
+ 110 ZB ZA 11 43 ZAC 7 RPC
L3235N
AC Characteristic A simplified AC model of the transmission circuits is shown in figure 13 Where: is the received signal Vrx Vtx is the transmitted signal Vl is the AC transversal voltage in line EG is the line open circuit AC voltage is the line impedance ZL RP are the protection resistors ZB is the line impedance balancing network ZA is the SLIC impedance balancing network ZAC programmable AC line termination impedance used for external protection resistors RPC insertion loss compensation is the AC transversal current divided by 50 Il/50 CAC AC feedback current decoupling AC behavior The AC path simplified formulas, that are valid when Il/50' is equal to Il/50, are the following : Two wire impedance The impedance presented to the two wire by the SLIC including the protection resistors RP and defined as Zs is equal to : Zs = ZAC/12.5 + 2RP i.e. with ZAC = 6250 W and Rp = 50 W Zs = 600 W Two wire to four wire gain The transmission gain , Gtx, of the SLIC is
equal to : GTX = Vtx / Vl GTX = 0.25 * (RPC + ZAC) / (25RP + ZAC) using RPC = 25RP , as recommended to compensate the protection resistor RP, GTX = 0.25 (-12 dB) Four wire to two wire gain The receiver gain , Grx, of the SLIC is equal to: GRX = Vl / Vrx GRX = 50Zl / (ZAC +12.5(Zl + 2RP)) using ZAC = 12.5(Zs - 2RP) and assuming Zl = Zs we have the following gain: GRX = 2 (+6 dB)
Hybrid function The transybrid loss, Thl, is equal to: Thl = Vtx / Vrx Thl = ZB / (ZA + ZB)-(ZAC +RPC) / (ZAC + + 12.5(2RP + Zl)) using ZAC = 12.5(ZS - 2RP) and RPC = 25RP we have the following relation: Thl = ZB / (ZA + ZB) - Zl / (Zl + Zs) To maximize the hybrid attenuation the impedance must be matched, ZA / ZB = ZS / Zl, to guarantee Thl = 0. From the above relation it is evident that if Zs is equal to the Zl in Thl test the impedance ZA and ZB can be substituted by two equal resistors.
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L3234 - L3235N
External components list for L3235N To set the SLIC into operation the following parameters have to be defined: - The AC SLIC impedance at line terminals "Zs" to which the return loss measurements is referred. It can be real (typ. 600) or complex. - The equivalent AC impedance of the line "Zl" used for evaluation of the trans-hybrid loss performance (2/4 wire conversion). It is usually a complex impedance. - The value of the two protection resistors Rp in series with the line termination. Once, the above parameters are defined, it is possible to calculate all the external components using the following table. The typical values has been obtained supposing: Zs = 600; Zl = 600; Rp = 50
Name RF CF RGF CGF RR RLIM CR RP RT CAC RPC ZAC CC ZAS RAS ZB CH CTX D1, D2 Text Suggested Value 39K 390nF 39K 390nF 51K 8.4K to 33K 4.7F 6.3 V 30% 50 1M 20% 100F 6.3V 20% 1250 1% 6250 1% 470pF 20% 12500 1% 2500 1% 15K 1% 220pF 20% 4.7F 30% 1N4007 (3) Function Delay Time On-hook Off-hook Delay Time GK Detector Bias Set Ext. Current Limit. Progr. Negative Battery Filter Protection Resistors Termination Resistor DC/AC current feedback splitting RP insertion loss compensation 2W AC Impedance programmation AC Feedback compensation Slic Impedance Balancing Net. Line impedance Balancing Net. CC Transybrid loss Compensation DC Decoupling Tx Output Line Rectifier External Transistor 5V supply filter VBAT supply filter Formula = 0.69 CF 39K = 0.69 CGF 39K 564 ILIM - 3mA (1)
RLIM = CAC =
1 2 16K fp 47 < RP < 100 (2)
1 2 220 fsp RPC = 12.5 (2RP) ZAC = 12.5 (ZS - 2RP) CAC = f1 = 300KHz 1 2f1 25RP ZAS = 25 (ZS - 2RP) RAS = 25 (2RP) ZB = 25 Zl ZAC C H = CC ZAS CC = 1 6.28 fp Zload
CTX =
PDiss > 2W, VCEO > 60V HFE > 40, IC > 100mA VBE < 0.8V @ 100mA
CVSS; CVDD CVB
100nF 100nF/100V
Notes: 1) For proper operation Cf should be selected in order to verify the following conditions: A) cf > 150nF B) < 1/2 * fRING fRING: Ringing signal frequency 2) For protection purposes the RP resistor is usually splitted in two part RP1 and RP2, with RP1 > 30. 3) ex: BD140; MJE172; MJE350.... (SOT32 or SOT82 package available also for surface mount). For low power application (reduced battery voltage) BCP53 (SOT223 surface mount package) can be used. Depending on application enviroment an heatsink could be necessary.
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L3234 - L3235N
Figure 13: Typical Appication Circuit Including L3234 and Protection
17/25
L3234 - L3235N
ELECTRICAL CHARACTERISTICS (Test condition: refer to the test circuit of the fig. 16; VCC = 5V, VSS = -5V, Vbat = -48V, Tamb = 25C, unless otherwise specified) Note: Testing of all parameters is performed at 25C. Characterization, as well as the design rules used allow correlation of tested performance with actual performance at other temperatures. All parameters listed here are met in the range 0C to +70C.
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
STAND-BY
Vls ILCC Output Voltage at TIP/RING pins Short Circuit Current ILINE = 0 Stand-by, SBY = 1 35.7 2 3 39 4 V mA
DC OPERATION
VlP Ilim Ilim IO If Ilgk Gklim Gkov Imax IVCC IVSS IVbat Output Voltage at TIP/RING pins Current Progr. Current Progr. On-hook Threshold Off-hook Threshold GK Detector Threshold Ground Key Current Limitation Ground Key Threshold Overloap Max. Output Current at TIP/RING Supply Current from VCC Supply Current from VSS Supply Current from Vbat ILINE = 0 ILINE = 50mA Ilim Prog. = 70mA 8.4K < RLIM < 33K 35.7 35.2 63 20 10 10 13 1 90 6.2 1.6 2.8 140 8 2.1 3.6 39 39 77 70 5 17 22 V V mA mA mA mA mA mA mA mA mA mA mA
70
RING to BGND Gklim-Ilgk Ilim = 70mA Iline = 0 Iline = 0 Iline = 0
AC OPERATION
Ztx Zrx Rl Thl Gs Gsf Gsl Gr Grf Grl Np4W Np2W Svrr Svrr Sending Output Impedance Receiving Input Impedance 2W Return Loss Trans Hybrid Loos Sending Gain Flatness Linearity Receiving Gain Flatness Linearity Psoph. Noise at Tx Psoph. Noise at Line Relative to Vbat versus Line Terminal versus Tx Terminal Relative to Vcc and Vss versus Line Terminal versus Tx Terminal L/T Conversion measured at line Terminals T/L Conversion Measured at Line Terminals pin 9 (Tx) pin 12 (Rx) f = 300 to 3400Hz f = 300 to 3400Hz f = 1020Hz Il = 20mA f = 300 to 3400Hz -20dB to 10dBm f = 1020Hz Il = 20mA f = 300 to 3400Hz -20dBm to +4dBm 10 1 22 22 -11.9 -0.2 -0.2 5.8 -0.2 -0.2 36 36 -12.1 M dB dB dB dB dB dB dB dB dBmp dBmp dB dB dB dB dB dB dB
6
f = 1020Hz VS = 100mVpp f = 1020Hz VS = 100mVpp f = 300 to 3400 Iline = 20mA f = 300 to 3400 Iline = 20mA 49 53(*) 46(*)
-90 -82 -30 -24 -20 -14
-12.3 0.2 0.2 6.2 0.2 0.2 -78 -70
A1 A2 A3
A4
A5
Ltc Tlc
A6 A7
(*) Selected parts L3235NC
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L3234 - L3235N
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
DIGITAL STATIC INTERFACE
Vil Vih Iil Iih Vol Voh Input Voltage at Logical "0" Input Voltage at Logical "1" Input Current at Logical "0" Input Current at Logical "1" Output Voltage at Logical "0" Output Voltage at Logical "1" Input SBY, CS1 Input SBY, CS1 Input SBY, CS1 Input SBY, CS1 Iout = 1mA Iout = 10A Iout = 10A Iout = 1mA 4 2.7 0 2 0.8 5 10 10 0.5 0.4 V V A A V V V V
Figure 14: Test Circuit
L3235N
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L3234 - L3235N
APPENDIX A L3235N TEST CIRCUITS Referring to the test circuit reported in fig 16 you can find the proper configuration for the main measurements. Figure A1: 2W Return Loss In particular: A-B: Line terminals C: Tx sending output on 4W side D: Rx receiving input on 4W Side
100F
100F
RL = 20 log
| ZML - Z | | 2VS | = 20 log | ZML + Z | |E|
Figure A2: Trans-hybrid Loss
100F
THL = 20log
VS
VR
100F
Figure A3: Sending Gain
100F
100F
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L3234 - L3235N
TEST CIRCUITS (continued) Figure A4: Receiving Gain
100F
100F
Figure A5: SVRR Relative to Battery Voltage VB
100F
100F
Figure A6: Longitudinal to Transversal Conversion
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L3234 - L3235N
Figure A7: Transversal to Longitudinal Conversion
APPENDIX B LAYOUT SUGGESTIONS Standard layout rules should be followed in order to get the best system performances:
1) Use always 100nF filtering capacitor close to the supply pins of each IC. 2) The L3235N bias resistor (RR) should be connected close to the corresponding pins of L3235N (REF and AGND).
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L3234 - L3235N
mm MIN. A C D D1 E F F1 G G1 G2 H2 H3 L L1 L2 L3 L5 L6 L7 M V2 Dia 3.65 2.41 4.91 7.49 9.2 10.05 4.6 3.9 6.55 5.9 2.6 15.1 6 0.17 4.1 6.75 6.1 2.8 2.54 5.08 7.62 2.4 1.2 0.35 0.6 TYP. MAX. 4.8 1.37 2.8 1.35 0.55 0.8 0.9 2.67 5.21 7.8 10.4 10.4 5.05 4.3 6.95 6.3 3 15.8 6.6 0.32 3.85 0.095 0.193 0.295 0.362 0.396 0.181 0.153 0.253 0.232 0.102 0.594 0.236 0.007 0.144 0.161 0.265 0.240 0.110 0.100 0.200 0.300 0.094 0.047 0.014 0.024 MIN. inch TYP. MAX. 0.189 0.054 0.110 0.053 0.022 0.031 0.035 0.105 0.205 0.307 0.409 0.409 0.198 0.170 0.273 0.248 0.118 0.622 0.260 0.012 0.152
DIM.
OUTLINE AND MECHANICAL DATA
8(max)
Heptawatt (Surface Mount)
April 1999
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L3234 - L3235N
mm MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030 0.055 0.014 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
DIM.
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B
C
e
L
K
TQFP4410
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L3234 - L3235N
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